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sy88083l 1g to 12.5g limiting post amplifier with digital offset correction revision 1.0 . micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com november 8 , 20 13 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 general description the sy88 083l limiting post amplifier is designed for use in fiber - optic receivers for continuous mode, mul ti - rate applications from 1gbps to 12.5gbps. the sy88 083l contains a high - bandwidth, high - sensitivity input stage with user - programmable, w ide - range sd a ssert/ los d e-a ssert threshold levels, which enables optimized system reach. typically, 4db of electrical hysteresis is provided to minimize los or sd chattering caused by noisy input signals. a logic level control pin is provided to enable user selection of an open - collector , ttl - compatible los or sd status indication signal with an external 5k to 10k pull - up resistor. the sy88 083l provides fast er sd a ssert and los de- a ssert times than typical continuous mode devices over the entire differential input voltage range of 10 mv pp to 1800mv pp . the sy88 083l input stage also provides a user - selectable digital offset correction (doc) function to automatically compensate for internal device offsets in the high - speed data path . the sy88 083l provides integrated 50 input and output impedances to optimize the high - speed signal paths and reduce component count . a ttl - compatible jam input is provided to enable a squelch function by feeding back the los or sd signal. the jam input disables only the post amplifier output. the sy88 083l operates from a single +3.3v power supply, over temperatures ranging from C 40 c to +85 c. datasheets and support documentation are available on micrels web site at: www.micrel.com . features ? multi - rate operation from 1.0625g bps to 12.5gbps ? selectable digital offset correction for internal offset compensa tion in the high - speed data path ? wide differential input range (10 mv pp to 1800mv pp ) ? wide sd de-a ssert or los assert threshold range ? 4.5 mv pp to 30mv pp ? 4db typical electrical hysteresis ? fast sd assert and los d e-a ssert times ? 1s typical; 2 s m aximum ? selectable los or sd status signal indicator ? ttl - compatible jam input with internal pull - up ? low - noise cml data inputs with integrated 50 termination impedance to internal reference v ref ? low - noise cml data outputs with integrated 50 termination impedance ? 30 ps typical rise/fall times ? wide range power supply: 3.3v 10% ? industrial temp erature range: ? 40 c to +85c ? available in a tiny 3 mm 3mm qfn package applications ? 10g/ 8g fibre channel ? 10gigabit ethernet ? otn equipment ? sonet oc192; sdh stm64 ? wdm/dwdm syste ms markets ? fibre channel storage area n etworks ? datacom/enterprise ? high - performance computing ? telecom ? wireless base s tations downloaded from: http:///
micrel, inc. sy88083l november 8 , 20 13 2 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 typical application circuit ordering information part number package type operating range package marking lead finish sy88083lm g 3 mm 3mm qfn - 16 industrial 083l with pb - free bar - line indicator nipdau pb - free sy88083lm g tr ( 1 ) 3mm 3mm qfn - 16 industrial 083l with pb - free bar - line indicator nipdau pb - free note: 1. tape and reel . downloaded from: http:///
micrel, inc. sy88083l november 8 , 20 13 3 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 p in configuration 16 - pin 3mm 3mm qfn (top view) downloaded from: http:///
micrel, inc. sy88083l november 8 , 20 13 4 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 pin description pin number pin name pin type pin function 1 gnd negative supply rail negative s upply r ail. connect to the pcb negative power supply plane that is also connected to the epad . 2 rxin+ high - speed data input differen tial n oninverting data i nput. lvp ecl/cml compatib le. ac- coupled with 1 0 0nf (high - frequency, low - esr cap acitor is recommended) . internally terminated with 50 to v cc C 0.9 v. ac- coupled only. 3 rxin ? high - speed data input dif ferential i nverting data i n put. lvpecl/ cml - compatible. ac -c oupled with 10 0 nf (high - frequency, low - esr cap acitor is recommended) . i nternally terminated by 50 to v cc C 0.9 v. ac- coupled only. 4 gnd negative supply rail negative supply r ail. connect to the pcb negative power supply plane that is also connected to the ep ad . 5 nc no connect no connect. do not connect to logic circuits or power supply rails. 6 nc no connect no connect. do not connect to logic circuits or power supply rails. 7 sd/los open collector logic output output status indicator. loss - of -s ignal (los) or s ignal d etect (sd) open collector output externally terminated with 5k to 10k resistor to v cc . ttl compatible. los = high when rxin amplitude falls below the threshold set at the sd/loslvl pin. sd = low when rxin amplitude falls below the threshold set at the sd/loslvl pin. 8 sd/ loslvl analog input analog control input. sets the trigger threshold for the los or sd status indicator signals. if sd/los_ sel = high (los selected), connect a resistor from the sd/loslvl pin (loss of s ignal threshold level) to v cc to adjust the los_assert threshold for the rxin data inputs. if sd/los _sel = low (sd selected), connect a resistor from the sd/ loslvl pin ( signal detect threshold l evel) to v cc to adjust the s d_d e- assert threshold for the rxin data inputs. 9 , 12 v cc positive supply rail positive power supply input. bypass with a 0.1 f capacitor in parallel with a 0.01 f low - esr capacitor to gnd as close as possible to the v cc pin. 10 rxout ? high - speed data output differential i nverting data o utput . cml compatible and internally terminated by 50 to v cc . can be ac - or dc - coupled to downstream devices. 11 rxout+ high - speed data output differential noninverting d ata o utput . cml compatible and internally terminated by 50 to v cc . can be ac - or dc - coupled to downstream devices. 13 test test pin factory test pin. for factory use only. do not connect to logic circuits or power supply rails. 14 sd/los _sel logic level input input control signal . ttl - compatible logic input signal to select los or sd as the output signal. internal ~18k pull - up to v cc . default = high (nc): los selected C normal operation los/sd _sel = low: sd selected and jam operation is inverted 15 jam logic level input input control signal. ttl - compatible input signal that enables or disables the rxout output signals. internal 2 7k pull - up resistor to v cc . can be connected to sd/los to form a squelch function. when sd/los _sel = high default = high and rxout outputs are disabled. low = rxout o utputs are enabled operation is inverted when sd/los _sel = low and sd is selected. downloaded from: http:///
micrel, inc. sy88083l november 8 , 20 13 5 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 pin description (continued) pin number pin name pin type pin function 16 doc_en logic level input input c ontrol signal. ttl -c ompatible logic input signal that enables or disables the d igital o ffset c orrection (doc) circuit. default: doc_en = high = enable with internal 18k pull - up to v cc if not connected to an external logic low or high s ignal. doc_en = low disables the digital offset c orrection function. toggling the doc_en signal from high t o lo w to h igh will cause a r eset of the doc circuitry and initiate a new doc routine to lock in new doc values. note : digital o ffset c orrection is not applied to large input signals . epad gnd negative supply rail exposed thermal pad. must be soldered to pcb plane connected to the negative supply rail. the recommended via array is needed to remove heat from the device. downloaded from: http:///
micrel, inc. sy88083l november 8 , 20 13 6 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 absolute maximum ratings ( 2 ) supply voltage (v cc ) ......................................... 0v to +4.0v input voltage (rxin ) .............................. v cc C 1.5v to v cc cml output voltage (v out ).. .. v cc ? 1.0v to v cc + 0.5v jam voltage ........................................................... 0 to v cc sd/loslvl voltage ................................ v cc C 1.3v to v cc le ad temperature (soldering, 20s ) ............................ 260c storage temperature (t s ) ......................... C 65c to +150c operating ratings ( 3 ) supply voltage (v cc ) .................................... +3.0v to +3.6v ambient temperature (t a ) .......................... C 40c to +85c junction temperature (t j ) ........................ C 40c to +120 c package thermal resistance ( 4 ) qfn ( ja ) still -a ir ............................................... 60c/w qfn ( jb ) ........................................................... 33c/w dc electrical characteristics v cc = 3.0 to 3.6v; t a = C 40c to +85c, typical values at v cc = 3.3v, t a = 25c. symbol parameter condition min . typ . max . units i cc power supply current note 5 60 75 ma sd/loslvl sd or los threshold voltage v cc ? 1.3 v cc v v oh rxout high voltage v cc ? 0.020 v cc ? 0.005 v cc v v ol rxout low voltage v cc ? 0.400 v cc ? 0.350 v cc ? 0.300 v v os_doc_on differential output offset digital offset correction = on 10 mv z 0 single - ended output impedance 45 50 55 z i single - ended input impedance 45 50 55 notes: 2. permanent device damage may occur if absolute maximum ratings are exceeded. this is a str ess rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this datasheet. exposur e to absolute max imum ratings conditions may affect device reliability . 3. the datasheet limits are not guaranteed if the device is operated beyond the recommended operating conditions. 4. package t hermal r esistance assumes that the exposed pad is soldered (or equivalent) to the devices most negative potential on the pcb. jb and ja assumes still air and a 4 - layer pcb, unless otherwise stated. it also a ssumes that the recommended via pattern and via sizes on the pcb are used . 5. doc is enabled, outputs rxout are loaded with external 50 loads , and the outpu ts are enabled. downloaded from: http:///
micrel, inc. sy88083l november 8 , 20 13 7 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 ttl dc electrical characteristics v cc = 3.0 to 3.6v; t a = C 40c to +85c, typical values at v cc = 3.3v, t a = 25c. symbol parameter condition min . typ . max . units v ih jam, doc_en, sd/los_sel input high voltage 2.0 v v il jam, doc_en, sd/los_sel input low voltage 0.8 v i ih jam, doc_en, sd/los_sel input high current v in = 2.7v 20 a v in = v cc 100 i il jam, doc_en, sd/los_sel input low current v in = 0.4v ? 0.3 ma v oh sd or los output high level sourcing 100a 2.4 v v ol sd or los output low level sinking 2ma 0.4 v downloaded from: http:///
micrel, inc. sy88083l november 8 , 20 13 8 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 ac electrical characteristics v cc = 3.3v 10%, t a = C 40c to +85c. typical values at v cc = 3.3v, t a = 25c; r load = 50? to v cc . symbol parameter condition min . typ . max . units t r , t f output rise/fall time (20% to 80%) note 6 30 45 ps t jitter deterministic note 7 10 ps random note 8 1 v id differential input voltage swing note 10 . see figure 1 . 10 1800 mv pp v od differential output voltage swing note 6 600 700 800 mv pp t los_d ; t los_a t sd_d; t sd_a los de -a ssert, los assert time sd de -a ssert, sd assert time note 11 1 2 u s los am_10k medium los assert level r loslvl = 10k ?, note 9 4.5 mv pp los dm_10k medium los de - assert level r loslvl = 10k ?, note 9 7.3 mv pp hys m_10k medium los hysteresis r loslvl = 10k ?, note 12 2 4.1 6 db los ah1_1k high1 los assert level r loslvl = 1k ?, note 9 18.6 mv pp los dh1_1k high1 los de - assert level r loslvl = 1k ?, note 9 28.3 mv pp hys h1_1k high1 los hysteresis r loslvl = 1k ?, note 12 2 3.6 6 db los ah2_100 high2 los assert level r loslvl = 100?, note 9 29.7 mv pp los dh2_100 high2 los de - assert level r loslvl = 100?, note 9 44.6 mv pp hys h2_100 high2 los hysteresis r loslvl = 100?, note 12 2 3.5 6 db a v(diff)_06 3c differential voltage gain 44 db s 21_06 3c single - ended small - signal gain 32 38 db t doc_delay doc delay time 15 s t doc_lock doc lock time 150 s note: 6. amplifier is in limiting mode. input is a 200mhz square wave. 7. deterministic jitter is measured using 10gbps k28.5 pattern, v id = 20mv pp . 8. random jitter is measured using 10gbps k28.7 pattern, v id = 20mv pp . 9. see typical operating characteristics for a graph showing how to choose a particular r loslvl for a particular los assert and its associated de - assert amplitude. 10. differential input swing amplitude for data rates up to 1 2.5gbps 11. in re al world applications, the los d e- assert/a ssert time can be strongly influenced by the rc time constant of the ac - coupling cap acitor and the 50 input termination. to keep this time low, use a decoupling cap acitor with the lowest value that is allowed by the data rate and the number of consecutive identical bits in the application (typical values are in the range of 0.001f to 0.1 f). 12. this specification defines electrical hysteresis as 20log (los de -a ssert/los a ssert). the ratio between optical hysteresis and electrical hysteresis is found to vary between 1.5 and 2 , depending on the level of received optical power and rosa characteristi cs. downloaded from: http:///
micrel, inc. sy88083l november 8 , 20 13 9 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 typical operating characteristics v cc = 3.3v, t a = 25c, r load = 50? to v cc , unless otherwise stated. 20 ps/div, typical 10.3g output with 10mv pp input signal 20 ps/div, typical 12.5g output with 10mv pp input signal 1 10 100 10 100 1000 10000 100000 input signal amplitude (mv pp ) sd/loslvl resistor ( ?) v id (los assert) and v id (los de - assert) vs. r sd/loslvl 0.00 1.00 2.00 3.00 4.00 5.00 6.00 10 100 1000 10000 100000 hysteresis (db) sd/loslvl resistor ( ?) los hysteresis vs. loslvl resistor downloaded from: http:///
micrel, inc. sy88083l november 8 , 20 13 10 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 functional block diagram downloaded from: http:///
micrel, inc. sy88083l november 8 , 20 13 11 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 functional description the sy88 083l is a high - sensitivity, high - bandwidth limiting post amplifier . it operates from a single +3.3v power supply across the entire industrial temperature range of C 40c to +85c. signals with data rates from 1.0625g bps to 12.5g bps and amplitudes as small as 10 mv pp are supported. figure 1 shows the allowed input voltage swing. rxin+ rxin- v is (mv) 5 (mv) 900 (mv) (rxin+) C (rxin-) v id (mv pp ) 10 (mv pp ) 1800 (mv pp ) figure 1. v is and v id definition the sy88 083l has a selectable sd or los status output signal that can be fed back to the jam input to perform the squelch function for output stability if there is no signal at the input. sd/loslvl sets the sensitivity of the input amplitude detection. the sy88 083l h as a user - selectable, integrated digital offset correction function to cancel internally generated output offsets. input amplifier/buffer figure 2 sho ws a simplified schematic of the input stage. the high sensitivity of the input amplifier allows signals as small as 10 mv pp to be detected and amplified. the input amplifier allows input signals as large as 1800mv pp . input small signals are amplified with a typical 44db differential voltage gain . output buffer the sy88 083l cml output buffer is designed to drive 50? impedance transmission lines and is internally terminated with 50? to v cc . figure 3 shows a simplified schematic of the output stage . signal detect/loss -of- signal (sd/los) the sy88 083l generates a user - selectable (sd/los_sel pin) signal detect (sd) or l oss - of -s ignal (los) open - collector ttl output , as shown in figure 4 . los is used to determine whether the input amplitude is too small to be considered as a valid input. l os asserts high if the input amplitude falls below the threshold set by sd/loslvl and de - asserts low otherwise. los can be fed back to the jam input to perform the squelch function and to maintain output stability under a los condition. jam de - asserts the true output signal low without removing the input signals. typically, 4db los hysteresis is provided to prevent chattering. when sd/los _sel is used to select the sd output on the sd/los pin, sd is a sserted when the differential input signal amplitude exceeds the level set by the sd/loslvl resistor. the jam operation is inverted when sd is selected. signal detect/ loss - of - signal level setting a programmable sd/los level set pin (sd/loslvl) sets the threshold of the input amplitude detection. connecting an external resistor between v cc and sd/loslvl sets the threshold voltage. this voltage ranges from v cc to v cc ? 1.3v. the external resistor creates a voltage divider between v cc and v cc ? 1.3v, as shown in figure 5 . hysteresis the sy88 083l provides typically 4db los electrical hysteresis, which is defined as 20log (vin los_de-assert vin los_assert ). because the relationship of the voltage output of the rosa to optical power at its input is linear, the optical hysteresis is typically half of the electrical hysteresis reported in the datasheet . i n practice the ratio between electrical and optical hysteresis is found to be between 1.5 and 1.8. thus , 4db elect rical hysteresis correspond s to an optical hysteresis within the range of 2 db to 2.4db. digital offset correction (doc) the digital offset correction (doc) circuit compensates for the inherent offsets found in high - gain amplifier circuits and minimizes the offset seen at the outputs. doc is a user - selectable feature using the doc_en pin as defined in the pin description table. conventional analog offset compensation techniques may be susceptible to drift from long continuous identical digit (cid) patterns. they can also add additional cost due to the extra dac and manufacturing setup time needed to optimize each individual module. the sy88 083l avoids both of these issues and provides a performance/cost optimized solution. the doc circuitry automatically detects any internal device offsets and locks the correction values but does not apply offset correction to large input signals. the doc is enabled by default unless doc_en is pulled low by an external logic level signal. it can be reset by toggling the doc_en pin high - to - low - to - high. the doc reset routine typically completes in 200 s. downloaded from: http:///
micrel, inc. sy88083l november 8 , 20 13 12 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 functional circuit structure s figu re 2. input structure figure 3. output structure downloaded from: http:///
micrel, inc. sy88083l november 8 , 20 13 13 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 functional circuit structures (continued) figure 4 . sd/los output structure figure 5 . sd/loslvl setting circuit related product and support documentation document number title application note link an- 45 notes on sensitivity and hysteresis in micrel post amplifiers www.micrel.com/_pdf/hbw/app - notes/an - 45.pdf sy88073l_83l_eb sy88073l/sy88083 l evaluation board http://www.micrel.com/_pdf/eval - board/sy88073l_83l_eb.pdf downloaded from: http:///
micrel, inc. sy88083l november 8 , 20 13 14 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 package information ( 12 ) 16 - pin (3mm 3mm) qfn - 16 note: 13. package information is correct as of the publication date. for updates and most current information, go to www.micrel.com . downloaded from: http:///
micrel, inc. sy88083l november 8 , 20 13 15 revision 1.0 hbwhelp@micrel.com or (408) 955 - 1690 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http://www.micrel.com micrel makes no representations or warranties with respect to the accuracy or co mpleteness of the information furnished in th is data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in micrels terms and conditions of sale for such products, mic rel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or us e of micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any pat ent, copyright or other intellectual property right . micrel products are not designed or authorized for use as components in life support appliances , devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are device s or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or systems is a purchasers own risk a nd purcha ser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 20 13 micrel, incorporated. downloaded from: http:///

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